library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity siggen2 is
    Port (  clock : in std_logic;   -- Internal Clock
            extclk: in std_logic;   -- External Clock
            clkout: out std_logic;  -- Clock Output -> clock
            hilo  : in std_logic;   -- Select clock
            dclk  : in std_logic;   -- Duty Shift Clock
            sdata : in std_logic;   -- Shift Data
            fclk  : in std_logic;   -- Frequency Shift Data
            enable: in std_logic;   -- Enable of Output
            sigout: out std_logic;  -- Signal Output
            cntout: out std_logic;  -- Output for Counter
            reset : in std_logic);  -- Master Reset
end siggen2;

architecture RTL of siggen2 is
    ---- Define Input Output Signal 
    signal  duty:   STD_LOGIC_VECTOR (20 downto 0);
    signal  sreg:   STD_LOGIC_VECTOR (20 downto 0);
    signal  count:  STD_LOGIC_VECTOR (20 downto 0);
    signal  freq:   STD_LOGIC_VECTOR (20 downto 0);
	 signal	comp:	  STD_LOGIC;
    signal  outff:  STD_LOGIC;
    signal  bcdcnt: STD_LOGIC_VECTOR (3 downto 0);
begin
    ---- Decimal counter for 1/10
    process (extclk) begin
        if (extclk' event and extclk = '1') then
            if (bcdcnt = "1001") then
                bcdcnt <= "0000";       -- Decimal
	            else
                bcdcnt <= bcdcnt + '1';
            end if;
        end if;
    end process;
    ---- Select Clock 1 or 1/10
    process (hilo) begin
        if (hilo = '0') then
            clkout <= extclk;
        else
            clkout <= bcdcnt(3);
        end if;
    end process;

    ---- Set Frequency Shift Register
    process (fclk, reset) begin
        if (reset = '1') then
            freq <= "000000000000000000000";
        elsif (fclk' event and fclk = '1') then
            freq <= freq (19 downto 0) & sdata;
        end if;
    end process;
    ---- Set Duty Shift Register
    process (dclk, reset) begin
        if (reset = '1') then
            duty <= "000000000000000000000";
        elsif (dclk' event and dclk = '1') then
            duty <= duty (19 downto 0) & sdata;
        end if;
    end process;

    ---- Main Counter
    process (clock, freq, count) begin
        if (count = freq) then
            count <= "000000000000000000000";
		elsif (clock' event and clock = '1') then
            count <= count +1;
        end if;
    end process;

    ---- Comparate and Output Control
    process (count, duty) begin
		if (count > duty) then
        	comp <= '1';
		else
         comp <= '0';
		end if;
    end process;
	 ---- Output Register Control
	 process (clock) begin
	 	if (clock' event and clock ='1') then
			outff <= comp;
		end if;
	end process;
    ---- Signal Output
    process (enable) begin
        if (enable = '1') then
            sigout <= outff;
        else
            sigout <= '0';
        end if;
    end process;
    ---- Counter output
    cntout <= outff;

end RTL;