library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ddsmain3 is Port ( sclk : in std_logic; sdata : in std_logic; set : in std_logic; square : out std_logic; reset : in std_logic; clock : in std_logic; daout : out std_logic_vector(5 downto 0)); end ddsmain3; architecture behavioral of ddsmain3 is ------------------------------- -- Define Internal Signal ------------------------------- signal sr: STD_LOGIC_VECTOR (17 downto 0); --Output of Shift Register signal frqlt: STD_LOGIC_VECTOR ( 17 downto 0); signal sum: STD_LOGIC_VECTOR (21 downto 0); --Output of Adder signal sumlt: STD_LOGIC_VECTOR (21 downto 0); --Output of Adder Latch signal tblout: STD_LOGIC_VECTOR (5 downto 0); --Output of Gate ---------------------------------------------- subtype WAVE is STD_LOGIC_VECTOR (5 downto 0); type ROM is array (0 to 63) of WAVE; constant SINE : ROM := ( "100000","100011","100110","101000","101011","101110","110001","110011", "110101","110111","111001","111011","111100","111101","111110","111110", "111111","111110","111110","111101","111100","111011","111001","110111", "110101","110011","110001","101110","101011","101000","100110","100011", "100000","011100","011001","010111","010100","010001","001110","001100", "001010","001000","000110","000100","000011","000010","000001","000001", "000001","000001","000001","000010","000011","000100","000110","001000", "001010","001100","001110","010001","010100","010111","011001","011100"); begin -------------------------------- -- Shift Register -------------------------------- process (sclk, reset) begin if (reset = '1') then sr <= "000000000000000000"; elsif (sclk' event and sclk = '1') then sr <= sr(16 downto 0) & sdata; end if; end process; ------------------------------- -- Frequency latch and change ------------------------------- process (set, reset) begin if (reset = '1') then frqlt <= "000000000000000000"; elsif (set' event and set = '1') then frqlt <= sr; end if; sum <= sumlt + ("0000" & frqlt); end process; -------------------------------- -- Latch Adder out -------------------------------- process (clock,reset) begin if (reset = '1') then sumlt <= "0000000000000000000000"; elsif (clock' event and clock ='1') then sumlt <= sum; end if; tblout <= SINE(CONV_INTEGER(sumlt (21 downto 16))); end process; --------------------------------- -- Get ROM Data and Latch and Output --------------------------------- process (clock) begin if (clock' event and clock = '0') then -- Square Wave out put(always out) square <= tblout(5); -- Sine Wave Output daout <= tblout; end if; end process; end behavioral;