library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dds6 is Port ( daout : out std_logic_vector(5 downto 0); clock : in std_logic); end dds6; architecture behavioral of dds6 is signal romadrs: std_logic_vector (5 downto 0); signal latch : std_logic_vector (5 downto 0); -- wave data subtype WAVE is STD_LOGIC_VECTOR (5 downto 0); type ROM is array (0 to 63) of WAVE; constant SINE : ROM := ( "100000","100011","100110","101000","101011","101110","110001","110011", "110101","110111","111001","111011","111100","111101","111110","111110", "111111","111110","111110","111101","111100","111011","111001","110111", "110101","110011","110001","101110","101011","101000","100110","100011", "100000","011100","011001","010111","010100","010001","001110","001100", "001010","001000","000110","000100","000011","000010","000001","000001", "000001","000001","000001","000010","000011","000100","000110","001000", "001010","001100","001110","010001","010100","010111","011001","011100"); begin process (clock) begin if (clock' event and clock = '1') then romadrs <= romadrs + '1'; end if; end process; process (clock) begin if (clock' event and clock = '0') then latch <= SINE(CONV_INTEGER ( romadrs )); end if; daout <= latch; end process; end behavioral;